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Philips Semiconductors
Product specification
PowerMOS transistor Logic level TOPFET
DESCRIPTION
Monolithic overload protected logic level power MOSFET in a surface mount plastic envelope, intended as a general purpose switch for automotive systems and other applications.
BUK107-50DL
QUICK REFERENCE DATA
SYMBOL VDS ID PD Tj RDS(ON) PARAMETER Continuous drain source voltage Continuous drain current Total power dissipation Continuous junction temperature Drain-source on-state resistance MAX. 50 0.7 1.8 150 200 UNIT V A W C m
APPLICATIONS
General controller for driving lamps small motors solenoids
FEATURES
Vertical power DMOS output stage Overload protected up to 85C ambient Overload protection by current limiting and overtemperature sensing Latched overload protection reset by input 5 V logic compatible input level Control of power MOSFET and supply of overload protection circuits derived from input Low operating input current permits direct drive by micro-controller ESD protection on all pins Overvoltage clamping for turn off of inductive loads
FUNCTIONAL BLOCK DIAGRAM
DRAIN
O/V CLAMP INPUT
RIG
POWER MOSFET
LOGIC AND PROTECTION
SOURCE
Fig.1. Elements of the TOPFET.
PINNING - SOT223
PIN 1 2 3 4 input drain source drain (tab) DESCRIPTION
PIN CONFIGURATION
4
SYMBOL
D TOPFET I
P
1
2
3
S
March 1997
1
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor Logic level TOPFET
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS ID II IIRM PD Tstg Tj PARAMETER Continuous drain source voltage Continuous drain current2 Continuous input current Non-repetitive peak input current Total power dissipation Storage temperature Continuous junction temperature
1
BUK107-50DL
CONDITIONS clamping tp 1 ms Tamb = 25 C normal operation3
MIN. -55 -
MAX. 50 self limiting 3 10 1.8 150 150
UNIT V A mA mA W C C
ESD LIMITING VALUE
SYMBOL VC PARAMETER Electrostatic discharge capacitor voltage CONDITIONS Human body model; C = 250 pF; R = 1.5 k MIN. MAX. 2 UNIT kV
OVERVOLTAGE CLAMPING LIMITING VALUES
At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients. SYMBOL EDSM EDRM PARAMETER Non-repetitive clamping energy Repetitive clamping energy CONDITIONS Tb 25 C; IDM < ID(lim); inductive load Tb 75 C; IDM = 50 mA; f = 250 Hz MIN. MAX. 100 4 UNIT mJ mJ
OVERLOAD PROTECTION LIMITING VALUES
With the protection supply provided via the input pin, TOPFET can protect itself from short circuit loads. Overload protection operates by means of drain current limiting and activating the overtemperature protection. SYMBOL VDDP PARAMETER CONDITIONS MIN. MAX. 35 16 UNIT V V Protected drain source supply voltage VIS = 5 V VIS = 4 V
OVERLOAD PROTECTION CHARACTERISTICS
TOPFET switches off to protect itself when there is an overload fault condition. It remains latched off until reset by the input. SYMBOL ID(lim) Tj(TO) PARAMETER Overload protection Drain current limiting VIS = 5 V 0.7 100 1.1 130 1.5 160 A C Overtemperature protection only in drain current limiting Threshold junction temperature VIS = 5 V CONDITIONS MIN. TYP. MAX. UNIT
1 Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy. 2 Refer to OVERLOAD PROTECTION CHARACTERISTICS. 3 Not in an overload condition with drain current limiting.
March 1997
2
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor Logic level TOPFET
THERMAL CHARACTERISTICS
SYMBOL Rth j-sp Rth j-b Rth j-a PARAMETER Thermal resistance Junction to solder point Junction to board1 Junction to ambient CONDITIONS MIN. -
BUK107-50DL
TYP. 12 40 -
MAX. 18 70
UNIT K/W K/W K/W
Mounted on any PCB Mounted on PCB of fig. 19
STATIC CHARACTERISTICS
Tb = 25 C unless otherwise specified SYMBOL V(CL)DSS V(CL)DSS IDSS IDSS IDSS RDS(ON) PARAMETER Drain-source clamping voltage Drain-source clamping voltage Off-state drain current Off-state drain current Off-state drain current Drain-source on-state resistance2 CONDITIONS VIS = 0 V; ID = 10 mA VIS = 0 V; IDM = 200 mA; tp 300 s; 0.01 VDS = 45 V; VIS = 0 V VDS = 50 V; VIS = 0 V VDS = 40 V; VIS = 0 V; Tj = 100 C VIS = 5 V; IDM = 100 mA; tp 300 s; 0.01 MIN. 50 TYP. 55 56 0.5 1 10 150 MAX. 70 2 20 100 200 UNIT V V A A A m
INPUT CHARACTERISTICS
Tb = 25 C unless otherwise specified. The supply for the logic and overload protection is taken from the input. SYMBOL VIS(TO) IIS IISL VISR V(CL)IS RIG PARAMETER Input threshold voltage Input supply current Input supply current Protection latch reset voltage3 Input clamping voltage Input series resistance CONDITIONS VDS = 5 V; ID = 1 mA normal operation; protection latched; VIS = 5 V VIS = 4 V VIS = 5 V VIS = 3.5 V MIN. 1.7 1 6 TYP. 2.2 330 170 500 250 2.2 7.5 33 MAX. 2.7 450 270 650 400 3.5 UNIT V A A A A V V k
II = 1.5 mA to gate of power MOSFET
SWITCHING CHARACTERISTICS
Tamb = 25 C; resistive load RL = 50 ; adjust VDD to obtain ID = 250 mA; refer to test circuit and waveforms SYMBOL td on tr td off tf PARAMETER Turn-on delay time Rise time Turn-off delay time Fall time VIS = 5 V to VIS = 0 V CONDITIONS VIS = 0 V to VIS = 5 V MIN. TYP. 8 30 3 6 MAX. UNIT s s s s
1 Temperature measured 1.3 mm from tab. 2 Continuous input voltage. The specified pulse width is for the drain current. 3 The input voltage below which the overload protection circuits will be reset.
March 1997
3
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor Logic level TOPFET
BUK107-50DL
120 110 100 90 80 70 60 50 40 30 20 10 0
PD%
Normalised Power Derating
a
Normalised RDS(ON) = f(Tj)
1.5
1.0
0.5
0
20
40
60
80 100 Tmb / C
120
140
0
-60 -40 -20
0
20
40 60 Tj / C
80
100 120 140
Fig.2. Normalised limiting power dissipation. PD% = 100PD/PD(25 C) = f(Tmb)
ID / A BUK107-50DL
CURRENT LIMITING OCCURS WITHIN THE SHADED REGION
Fig.5. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 C = f(Tj); ID = 100 mA; VIS = 5 V
RDS(ON) / mOhm 240 200 160 MAX. BUK107-50DL
2.0
1.5
TYP.
1.0
TYP.
120 80
0.5
40
0 0 20 40 60 80 Tamb / C 100 120 140
0 0 2 4 VIS / V 6 8 10
Fig.3. Continuous drain current. ID = f(Tamb); condition: VIS = 5 V
ID / A VIS / V = BUK107-50DL 7 6 1 5
Fig.6. Typical on-state resistance, Tj = 25 C. RDS(ON) = f(VIS); conditions: ID = 100 mA, tp = 300 s
ID / A BUK107-50DL
1.5
1.5
1
4 0.5 0.5
0 0 4 8 12 16 VDS / V 20 24 28 32
0 0 2 4 VIS / V 6 8 10
Fig.4. Typical on-state characteristics, Tj = 25 C. ID = f(VDS); parameter VIS; tp = 300 s
Fig.7. Typical transfer characteristics, Tj = 25 C. ID = f(VIS); conditions: VDS = 10 V, tp = 300 s
March 1997
4
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor Logic level TOPFET
BUK107-50DL
200 180 160 140
Tj(TO) / C
BUK107-50DL
VIS(TO) / V
BUK107-50DL
3 MAX. TYP.
TYP.
2 MIN.
120 100 80 60 0 2 4 VIS / V 6 8 10
1
-50
0
50 Tj / C
100
150
Fig.8. Typical overtemperature protection threshold. Tj(TO) = f(VIS); condition: VDS = 10 V
IIS & IISL / mA BUK107-50DL
Fig.11. Input threshold voltage. VIS(TO) = f(Tj); conditions: ID = 1 mA; VDS = 5 V
II / mA BUK107-50DL
1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0
10 9 8
LATCHED
7 6 5
NORMAL
RESET
IISL IIS
4 3 2 1 0
0
2
4 VIS / V
6
8
0
2
4 VIS / V
6
8
10
Fig.9. Typical DC input characteristics, Tj = 25 C. IIS & IISL = f(VIS); normal operation & protection latched
IIS / uA VIS / V = 400 BUK107-50DL
Fig.12. Typical input clamping characteristic. II = f(VIS); normal operation, Tj = 25 C.
ID / mA BUK107-50DL
500
200
150
5V 300
TYP. 100
200 4V 100
50
0 -50 0 50 Tj / C 100 150
0 50 52 54 VDS / V 56 58 60
Fig.10. Typical DC input current. IIS = f(Tj); parameter VIS; normal operation
Fig.13. Overvoltage clamping characteristic, 25 C. ID = f(VDS); conditions: VIS = 0 V; tp 300 s
March 1997
5
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor Logic level TOPFET
BUK107-50DL
VDD
10 uA
IDSS
BUK107-50DL
RL VDS TOPFET I
P
1 uA
D
measure
100 nA
D.U.T. S 0V
VIS
10 nA -50 0 50 Tj / C 100 150
Fig.14. Test circuit for resistive load switching times. VIS = 5 V
VIS & VDS / V BUK107-50DL
Fig.16. Typical drain source leakage current IDSS = f(Tj); conditions: VDS = 40 V; VIS = 0 V.
15
VDS 10
VIS 5
0 -20 0 20 40 60 80 100 time / us 120 140 160 180
Fig.15. Typical switching waveforms, resistive load . RL = 50 ; adjust VDD to obtain ID = 250 mA; Tj = 25C
1E+02
Zth j-amb / (K/W) D= 0.5 0.2 0.1 0.05 0.02
BUK107-50DL
1E+01
1E+00
P D
1E-01
tp
D=
tp T t
1E+03
T
1E-02 1E-07 0 1E-05 1E-03 t/s 1E-01 1E+01
Fig.17. Transient thermal impedance, TOPFET mounted on PCB of fig 19. Zth j-amb = f(t); parameter D = tp/T
March 1997
6
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor Logic level TOPFET
MOUNTING INSTRUCTIONS
Dimensions in mm.
3.8 min
BUK107-50DL
PRINTED CIRCUIT BOARD
Dimensions in mm.
36
1.5 min
18
60 9
2.3 1.5 min (3x) 6.3
4.6
4.5
10
1.5 min
4.6
7 15 50
Fig.18. Soldering pattern for surface mounting.
Fig.19. PCB for thermal resistance and power rating. PCB: FR4 epoxy glass (1.6 mm thick), copper laminate (35 m thick).
March 1997
7
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor Logic level TOPFET
MECHANICAL DATA
Dimensions in mm Net Mass: 0.11 g
handbook, full pagewidth
BUK107-50DL
0.95 0.85
S
seating plane 6.7 6.3 3.1 2.9
0.1 S
0.32 0.24
B 0.2 M A 4
A
0.10 0.01
3.7 3.3
o
7.3 6.7
16 o max
16
1 1.80 max 10 o max
2 0.80 0.60 4.6
3
2.3
0.1 M B (4x)
MSA035 - 1
Fig.20. SOT223 surface mounting package1.
1 For further information, refer to surface mounting instructions for SOT223 envelope. Epoxy meets UL94 V0 at 1/8".
March 1997
8
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor Logic level TOPFET
DEFINITIONS
Data sheet status Objective specification Product specification Limiting values
BUK107-50DL
This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. (c) Philips Electronics N.V. 1997 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
March 1997
9
Rev 1.200

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